Designers and manufacturers of electronic devices are continually searching for ways to reduce the size of electronic components. Some recent developments involve the use of solder connections for electrically interconnecting semiconductor chips to printed circuit boards ("PCB") in order to use the space on the PCB more efficiently. Solder connections have proven to be somewhat effective; however, the differences in thermal expansion and contraction ("thermal mismatch") between the semiconductor chip and the PCB places a great amount of stress on the solder and may adversely effect the integrity of the numerous solder bonds required to make an electrical connection. In addition, warpage of either the semiconductor chip or the PCB may have a negative effect on the integrity of the solder connections.
Several inventions, commonly assigned to the assignee of the present invention, deal effectively with the thermal mismatch problem. For example, one embodiment of U.S. Pat. No. 5,148,266 discloses a semiconductor chip which can be connected to a substrate using a sheet-like, and preferably flexible, interposer which overlies the top, contact-bearing surface of the chip. The interposer has terminals and includes flexible leads for interconnecting the contacts on the chip with the terminals on the interposer so that the terminals are movable relative to the contacts on the chip which provides excellent resistance to differential expansion of the chip relative to the substrate caused by thermal cycling. A compliant layer may be disposed between the interposer and the chip.
Commonly assigned U.S. Pat. No. 5,477,611, the disclosure of which is incorporated herein by reference, discloses a method for creating an interface between a chip and chip carrier, including spacing the chip a given distance above the chip carrier, and introducing a liquid in the gap between the chip and carrier. Preferably, the liquid is a curable material which is cured into a resilient layer such as an elastomer after its introduction into the gap. In one preferred embodiment, the terminals on a chip carrier are planarized or otherwise vertically positioned by deforming the terminals into set vertical locations with a plate, and a liquid is then cured between the chip carrier and chip.
Commonly assigned U.S. Pat. No. 5,548,091 describes other methods of bonding compliant elements to the chip and support structure using adhesives. In certain preferred methods according to the '091 patent, a support structure, such as a dielectric film, is provided with a prefabricated compliant layer which in turn has an adhesive on its surface remote from the dielectric film. The semiconductor chip is placed in contact with the adhesive, and the adhesive is activated to bond the chip to the compliant layer. The adhesive may be provided in a non-uniform layer to facilitate release of air during the bonding process and thus prevent void formation.
Copending, commonly assigned U.S. patent application Ser. No. 08/365,699 entitled "Compliant Interface for a Semiconductor Chip and Method Therefor" filed Dec. 29, 1994, the disclosure of which is incorporated herein by reference, discloses a method of fabricating a compliant interface for a semiconductor chip. In certain preferred methods according to the '699 application, a first support structure is provided and a resilient element, such as a plurality of compliant pads, is attached to a first surface of the first support structure. The plurality of compliant pads comprise an array of pads, whereby any two adjacent pads in the array define a channel therebetween. Attaching the array of compliant pads to the first support structure may be accomplished in a number of different ways. In one embodiment, a stencil mask having a plurality of holes extending therethrough is placed on top of the first surface of the support structure. The holes in the mask are then filled with a curable liquid, such as silicone. After the mask has been removed, the curable liquid is at least partially cured to form an elastomer including an array of compliant pads having channels between adjacent pads.
In a further preferred embodiment of the '699 application, the assembly including the plurality of compliant pads is used with a second support structure, such as a semiconductor chip having a plurality of contacts on a first surface. The first surface of the chip is abutted against the plurality of compliant pads and the contacts are electrically connected to a corresponding plurality of terminals on the support structure. The array of compliant pads assures coplanarity between the chip and the support structure. A compliant filler, such as a curable liquid, is allowed to flow into the channels between the chip and the support structure and around the compliant pads while the chip and support structure are held in place. The filler may then be cured to form a substantially uniform, planar, compliant layer between the chip and the support structure which effectively accommodates for the thermal coefficient of expansion mismatch between the chip and a supporting substrate.
Copending commonly assigned U.S. patent application Ser. No. 08/877,379 entitled "Bondable Compliant Pads for Packaging of a Semiconductor Chip and Method Therefor" filed Jun. 10, 1997 and U.S. Provisional Application Serial No. 60/019,475 filed Jun. 10, 1996, the disclosures of which are incorporated herein by reference, disclose a method of fabricating a compliant interface for a semi-conductor chip comprising a resilient element having one or more intermediary layers capable of being wetted by an adhesive. In one preferred embodiment according to the disclosure, a layer of fibrous material, such as paper, is provided at one or more surface regions of the curable elastomer and the elastomer is then cured while in contact with the paper. In another embodiment, a fibrous mesh or pad is provided at one or more surface regions of a curable elastomer. In further embodiments, a fibrous material is mixed with or blended into a curable elastomer and the elastomer is cured so that at least some of the fibrous material protrudes from the surface regions thereof. The resilient element provided by the disclosed methods can be used with an adhesive to bond the resilient element to one or more microelectronic elements. After curing of the adhesive, the adhesive engages and/or intermeshes with the one or more intermediary layers.
Despite the positive results of the aforementioned commonly owned inventions, the disclosures of which are incorporated herein by reference, still further improvements would be desirable.